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Final Electrical Specifications
LTC1654 Dual 14-Bit Rail-to-Rail DAC in 16-Lead SSOP Package
FEATURES
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April 2000
DESCRIPTIO
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14-Bit Monotonic Over Temperature Individually Programmable Speed/Power: 3.5s Settling Time at 750A 8s Settling Time at 450A Maximum Update Rate: 0.9MHz Smallest Dual 14-Bit DAC: 16-Lead Narrow SSOP Package Buffered True Rail-to-Rail Voltage Outputs 3V to 5V Single Supply Operation User Selectable Gain Power-On Reset and Clear Function Schmitt Trigger On Clock Input Allows Direct Optocoupler Interface
The LTC(R)1654 is a dual, rail-to-rail voltage output, 14-bit digital-to-analog converter (DAC). It is available in a 16-lead narrow SSOP package, making it the smallest dual 14-bit DAC available. It includes output buffer amplifiers and a flexible serial interface. The LTC1654 has REFHI pins for each DAC that can be driven up to VCC. The output will swing from 0V to VCC in gain of 1 configuration or VCC/2 in gain of 1/2 configuration. It operates from a single 2.7V to 5.5V supply. The LTC1654 has two programmable speeds: a FAST and SLOW mode with 1LSB settling times of 3.5s or 8s respectively and supply currents of 750A and 450A in the two modes. The LTC1654 also has shutdown capability, power-on reset and clear function to 0V.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s s s s
Digital Calibration Industrial Process Control Automatic Test Equipment Offset/Gain Adjustment
BLOCK DIAGRA
CS/LD SCK
CONTROL LOGIC
SDI
INPUT LATCH
DAC REGISTER
DAC B
+
VOUT B
-
32-BIT SHIFT REGISTER X1/X1/2 B REFHI A
INPUT LATCH
DAC REGISTER
DAC A
+
VOUT A
SDO POWER-ON RESET REFLO B REFLO A
-
X1/X1/2 A
1654 BD
CLR
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
REFHI B
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1
LTC1654
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW X1/X1/2 B CLR SCK SDI CS/LD DGND SDO X1/X1/2 A 1 2 3 4 5 6 7 8 16 VCC 15 VOUT B 14 REFHI B 13 REFLO B 12 AGND 11 REFLO A 10 REFHI A 9 VOUT A
VCC to GND .............................................. - 0.5V to 7.5V TTL Input Voltage, REFHI, REFLO, X1/X1/2 ........................................ - 0.5V to 7.5V VOUT, SDO .................................. - 0.5V to (VCC + 0.5V) Operating Temperature Range LTC1654C ............................................. 0C to 70C LTC1654I ........................................ - 40C to 85C Maximum Junction Temperature .......................... 125C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER LTC1654CGN LTC1654IGN
GN PART MARKING 1654 1654I
GN PACKAGE 16-LEAD NARROW PLASTIC SSOP
TJMAX = 125C, JA = 95C/ W
Consult factory for Military grade parts.
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, VCC = 2.7V to 5.5V, VOUT A, VOUT B unloaded, REFHI A, REFHI B = 4.096V (VCC = 5V), REFHI A, REFHI B = 2.048V (VCC = 2.7V), REFLO = 0V, X1/X1/2 = 0V.
SYMBOL DAC Resolution Monotonicity DNL INL ZSE VOS VOSTC Differential Nonlinearity Integral Nonlinearity Zero Scale Error Offset Error Offset Error Tempco Gain Error Gain Error Drift Power Supply VCC ICC Positive Supply Voltage Supply Current (SLOW/FAST) For Specified Performance 2.7V VCC 5.5V (Note 5) SLOW 2.7V VCC 5.5V (Note 5) FAST 2.7V VCC 3.3V (Note 5) SLOW 2.7V VCC 3.3V (Note 5) FAST In Shutdown (Note 5) VOUT Shorted to GND VOUT Shorted to VCC Input Code = 0 Input Code = 16383, VCC = 2.7V to 5.5V, VREF = 2.048V
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ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS
MIN 14 14
TYP
MAX
UNITS Bits Bits
Guaranteed Monotonic (Note 2) Integral Nonlinearity (Note 2) C Grade I Grade Measured at Code 50, C Grade Measured at Code 50, I Grade
q q q q q q
1 4 0 6.5 9.0 6.5 9.0 15 15 5 2.7 450 750 250 450 7 70 80 40 5.5 800 1300 500 900 30 120 120 200 2.25
ppm/C V A A A A A mA mA mV/V
Op Amp DC Performance Short-Circuit Current Low Short-Circuit Current High Output Impedance to GND Output Line Regulation
2
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LSB LSB mV mV mV mV V/C LSB
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LTC1654
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER Voltage Output Slew Rate Voltage Output Settling Time Digital Feedthrough Midscale Glitch Impulse Output Noise Voltage Density Digital I/O VIH VIL VOH VOL VIH VIL VOH VOL ILEAK CIN Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Digital Input Capacitance Reference Input Resistance Reference Input Range Reference Input Current Switching Characteristics (VCC = 4.5V to 5.5V) t1 t2 t3 t4 t5 t6 t7 t8 t9 t1 t2 t3 t4 t5 t6 t7 t8 t9 SDI Valid to SCK Setup SDI Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK to CS/LD CS/LD Low to SCK SD0 Output Delay SCK Low to CS/LD Low SDI Valid to SCK Setup SDI Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK to CS/LD CS/LD Low to SCK SDO Output Delay SCK Low to CS/LD Low (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) VCC = 5V VCC = 5V CONDITIONS AC Performance
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, VCC = 2.7V to 5.5V, VOUT A, VOUT B unloaded, REFHI A, REFHI B = 4.096V (VCC = 5V), REFHI A, REFHI B = 2.048V (VCC = 2.7V), REFLO = 0V, X1/X1/2 = 0V.
MIN
q q
TYP
MAX
UNITS V/s V/s
(Note 3) SLOW (Note 3) FAST (Note 4) to 1LSB, SLOW (Note 4) to 1LSB, FAST (Note 8) DAC Switch Between 8000 and 7FFF at 1kHz, SLOW at 1kHz, FAST
0.20 1.25 8.0 3.5 1 20 540 320
s s nV*s nV*s nV/Hz nV/Hz V 0.8 V V 0.4 V V 0.8 V V 0.4 10 10 V A pF k VCC 1 V A ns ns ns ns ns ns ns 100 ns ns ns ns ns ns ns ns ns 150 ns ns
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2.4 VCC - 0.75 2.4 VCC - 0.75
VCC = 5V, IOUT = - 1mA, DOUT Only VCC = 5V, IOUT = 1mA, DOUT Only VCC = 3V VCC = 3V VCC = 3V, IOUT = - 1mA, DOUT Only VCC = 3V, IOUT = 1mA, DOUT Only VIN = GND to VCC (Note 6) REFHI to REFLO (Notes 6, 7) In Shutdown
Reference Input
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30 0
60
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30 0 15 15 15 10 10 5 10 45 0 20 20 20 15 15 5 15
CLOAD = 100pF (Note 6)
Switching Characteristics (VCC = 2.7V to 5.5V)
q q q q q q q q q
CLOAD = 100pF (Note 6)
3
LTC1654
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Nonlinearity is defined from code 50 to code 16383 (full scale). See Applications Information. Note 3: 100pF Load Capacitor Note 4: DAC switched between code 200 and code 16383. Note 5: Digital inputs at 0V or VCC. Note 6: Guaranteed by design. Note 7: VOUT can only swing from (GND +VOS) to (VCC -VOS) when output is unloaded. See Applications Information. Note 8: CS/LD = 0, VOUT = 4.096 and data is being clocked in.
PI FU CTIO S
X1/X1/2 B, X1/X1/2 A (Pins 1, 8): The Gain of 1 or Gain of 1/2 Pin. When this pin is tied to VOUT, the output will swing up to REFHI/2 and when this pin is tied to REFLO, the output will swing up to REFHI. These pins should not be left floating. CLR (Pin 2): The Asynchronous Clear Input. SCK (Pin 3): The TTL Level Input for the Serial Interface Clock. SDI (Pin 4): The TTL Level Input for the Serial Interface Data. Data on the SDI pin is latched into the shift register on the rising edge of the serial clock. The LTC1654 requires a 24-bit word. The first 8 bits are control/address followed by 16 data bits. The last two of the 16 data bits are don't cares. If daisy-chaining is desired, then a 32-bit data word can be used with the first 8 being don't cares and the following 24 bits as above. CS/LD (Pin 5): The TTL Level Input for the Serial Interface Enable and Load Control. When CS/LD is low, the SCK signal is enabled, so the data can be clocked in. When CS/LD is pulled high, the control/address bits are decoded. DGND/AGND (Pins 6, 12): Digital and Analog Grounds. SDO (Pin 7): The output of the shift register that becomes valid on the rising edge of the serial clock. VOUT A/B (Pins 9, 15): The Buffered DAC Outputs. REFHI A/B (Pins 10, 14): The Reference High Inputs of the LTC1654. There is a gain of 1 from this pin to the output in a gain of 1 configuration. In a gain of 1/2 configuration, there is a gain of 1/2 from this pin to VOUT. REFLO A/B (Pins 11, 13): The Reference Low Inputs of the LTC1654. VCC (Pin 16): The Positive Supply Input. 2.7V VCC 5.5V. Requires a 0.1F bypass capacitor to ground.
TI I G DIAGRA S
t2 t1 SCK t9 SDI X X C3 B0 X X t5 CS/LD t8 SDO X (PREVIOUS WORD) X C3 X X X CURRENT WORD
1654 TD01
4
W
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UW
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t6 t4 t3 t7
24-Bit Update (Without Daisy-Chain)
TI I G DIAGRA S UW LTC1654
SCK 4 A3 A1 B12 B7 B2 B1 B6 B11 B10 B9 B8 A2 A0 B13 B5 X B4 B3 B0 X 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
SDI
C3
C2
C1
C0
32-Bit Update (Without Daisy-Chain)
CS/LD 6 15 A1 B13 B12 B10 B9 B11 A0 B8 16 22 X X C3 C2 C0 A3 A2 X C1 7 8 9 12 13 14 17 18 19 20 21 10 11 23 B7 24 B6 25 B5 26 B4 27 B3 28 B2 29 B1 30 B0 31 X 32 X
SCK
1
2
3
4
5
SDI
X
X
X
X
X
32-Bit Update (Can Daisy-Chain)
CS/LD 6 15 A1 A1 A0 A0 B13 B13 16 X X X C3 C2 C0 A3 A2 X C1 X C3 C2 C0 A3 A2 X C1 7 8 9 12 13 14 17 10 11 18 B12 B12 19 B11 B11 20 B10 B10 21 B9 B9 22 B8 B8 23 B7 B7 24 B6 B6 25 B5 B5 26 B4 B4 27 B3 B3 28 B2 B2 29 B1 B1 30 B0 B0 31 X X 32 X X X CURRENT WORD
1654 TD02
SCK
1
2
3
4
5
SDI
X
X
X
X
X
SDO
X
X
X
X
X
PREVIOUS WORD
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CS/LD
5
LTC1654
OPERATIO
Serial Interface
The data on the SDI input is loaded into the shift register on the rising edge of SCK. The MSB is loaded first. The Clock is disabled internally when CS/LD is high. Note: SCK must be low before CS/LD is pulled low to avoid an extra internal clock pulse. If no daisy-chaining is required, the input word can be 24-bit wide, as shown in the timing diagrams. The 8 MSBs, which are loaded first, are the control and address bits followed by a 16-bit data word. The last two LSBs in the data word are don't cares. The input word can be a stream of three 8-bit wide segments as shown in the "24-Bit Update" timing diagram. If daisy-chaining is required or if the input needs to be written in two 16-bit wide segments, then the input word can be 32 bits wide and the top 8 bits (MSBs) are don't cares. The remaining 24 bits are control/address and data. This is also shown in the timing diagrams. The buffered output of the internal 32-bit shift register is available on the SDO pin, which swings from GND to VCC. Multiple LTC1654s may be daisy-chained together by connecting the SDO pin to the SDI pin of the next IC. The SCK and CS/LD signals remain common to all ICs in the daisy-chain. The serial data is clocked to all of the chips, then the CS/LD signal is pulled high to update all DACs simultaneously. Table 1 shows the truth table for the control/address bits. When the supplies are first applied, the LTC1654 uses SLOW mode, the outputs are set at 0V, and zeros are loaded into the 32-bit input shift register. Three examples are given to illustrate the DAC's operation: 1. Load and update DAC A in FAST mode. Leave DAC B unchanged. Perform the following sequence for the control, address and DATA bits: Step 1: Set DAC A in FAST mode CS/LD CS/LD CS/LD clock in 0101 0000 XXXXXXXX XXXXXXXX;
Step 2: Load and update DAC A with DATA clock in 0011 0000 + DATA; CS/LD
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2. Load and update DAC A in SLOW mode. Power down DAC B. Perform the following sequence for the control, address and DATA bits: Step 1: Set DAC A in SLOW mode CS/LD CS/LD CS/LD CS/LD CS/LD clock in 0110 0000 XXXXXXXX XXXXXXXX; Step 2: Load and update DAC A with DATA clock in 0011 0000 + DATA; CS/LD clock in 0100 0001 XXXXXXXX XXXXXXXX; Step 3: Power down DAC B 3. Power down both DACs at the same time. Perform the following sequence for the control, address and DATA bits: Step 1: Power down both DACs simultaneously CS/LD CS/LD clock in 0100 1111 XXXXXXXX XXXXXXXX; Voltage Output The LTC1654 comes complete with rail-to-rail voltage output buffer amplifiers. These amplifiers will swing to within a few millivolts of either supply rail when unloaded and to within a 300mV of either supply rail when sinking or sourcing 5mA. There are two GAIN configuration modes for the LTC1654: a) GAIN of 1: (X1/X1/2 tied to REFLO) VOUT = (VREFHI - VREFLO)(SDI/16384) + VREFLO b) GAIN of 1/2: (X1/X1/2 tied to VOUT) VOUT = (1/2)(VREFHI - VREFLO)(SDI/16384) + VREFLO The LTC 1654 has two SPEED modes: A FAST mode and a SLOW mode. When operating in the FAST mode, the output amplifiers will settle in 3.5s (typ) to 14 bits on a 4V output swing. In the SLOW mode, they will settle in 8s. The total supply current is 750A in the FAST mode and 450A in the SLOW mode.
LTC1654
OPERATION
Power Down Each DAC can also be independently powered down to less than 5A/DAC of supply current. The reference pin also goes into a high impedance state when the DAC is powered down and the reference current will drop to below 0.1A. The amplifiers' output stage is also three-stated but the
Table 1.
CONTROL C3 C2 C1 C0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Load Input Register n Update (Power-Up) DAC Register n Load Input Register n, Update (Power-Up) All Load and Update n Power Down n Fast n (Speed States are Maintained Even If DAC is Put in Power-Down Mode) Slow n (Default State is Slow When Supplies are Powered Up) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) No Operation ADDRESS (n) A3 A2 A1 A0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DAC A DAC B Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Both DACs
INPUT WORD
CONTROL C3 C2 C1 C0 A3 ADDRESS A2 A1 A0 D13 D12 D11 D10 D9 DATA (14 + 2 DUMMY LSBs) D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
1654 TABLE
U
VOUT pins still have the internal gain-setting resistors connected to them resulting in an effective resistance from VOUT to REFLO. This resistance is typically 90k when the X1/X1/2 pin is tied to VOUT and 36k when X1/X1/2 is tied to REFLO. Because of this resistance, VOUT will go to VREFLO when the DAC is powered down and VOUT is unloaded.
7
LTC1654
APPLICATIONS INFORMATION
Rail-to-Rail Output Considerations In any rail-to-rail DAC, the output swing is limited to voltages within the supply range. If the DAC offset is negative, the output for the lowest codes limits at 0V as shown in Figure 2b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC . If VREF = VCC and the DAC full-scale error
VREF = VCC POSITIVE FSE
OUTPUT VOLTAGE
0
OUTPUT VOLTAGE
0V NEGATIVE OFFSET INPUT CODE (b)
1654 F02
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
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(FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 2c. No full-scale limiting can occur if VREF is less than (VCC - FSE). Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur.
OUTPUT VOLTAGE
INPUT CODE (c) VREF = VCC
8192 INPUT CODE (a)
16383
LTC1654
DEFI ITIO S
Resolution (n): Resolution is defined as the number of digital input bits (n). It is also the number of DAC output states (2n) that divide the full-scale range. Resolution does not imply linearity. Full-Scale Voltage (VFS): This is the output of the DAC when all bits are set to 1. Voltage Offset Error (VOS): Normally, DAC offset is the voltage at the output when the DAC is loaded with all zeros. The DAC can have a true negative offset, but because the part is operated from a single supply, the output cannot go below 0V. If the offset is negative, the output will remain near 0V resulting in the transfer curve shown in Figure 1. Zero-Scale Error (ZSE): The output voltage when the DAC is loaded with all zeros. Since this is a single supply part, this value cannot be less than 0V. Integral Nonlinearity (INL): End-point INL is the maximum deviation from a straight line passing through the end points of the DAC transfer curve. Because the part operates from a single supply and the output cannot go below zero, the linearity is measured between full scale and the code corresponding to the maximum offset specification. The INL error at a given input code is calculated as follows: INL = [VOUT - VOS - (VFS - VOS)(code/16383)]/LSB VOUT = The output voltage of the DAC measured at the given input code Differential Nonlinearity (DNL): DNL is the difference between the measured change and the ideal one LSB change between any two adjacent codes. The DNL error between any two codes is calculated as follows:
1654 F01
OUTPUT VOLTAGE
NEGATIVE OFFSET
Figure 1. Effect of Negative Offset
The offset of the part is measured at the code that corresponds to the maximum offset specification: VOS = VOUT - [(Code)(VFS)/(2n - 1)] Least Significant Bit (LSB): One LSB is the ideal voltage difference between two successive codes. LSB = (VFS - VOS)/(2n - 1) = (VFS - VOS)/16383 Nominal LSBs: LTC1654 LSB = 4.09575V/16383 = 250V
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DAC CODE
DNL = (VOUT - LSB)/LSB V OUT = The measured voltage difference between two adjacent codes Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in nV * s.
9
LTC1654
TYPICAL APPLICATION
Dual 14-Bit Voltage Output DAC
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2.7V TO 5.5V LTC1654 1 2 3 4 5 6 7 8 X1/X1/2 B CLR SCK SDI CS/LD DGND SDO X1/X1/2 A VCC VOUT B REFHI B REFLO B AGND REFLO A REFHI A VOUT A 16 15 14 13 12 11 10 9
1654 TA01
0.1F
OUTPUT B: 0V TO VCC
OUTPUT A: 0V TO VCC
LTC1654
PACKAGE DESCRIPTION U
Dimensions in inches (millimeters) unless otherwise noted. GN Package 16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 - 0.196* (4.801 - 4.978) 16 15 14 13 12 11 10 9
0.009 (0.229) REF
0.229 - 0.244 (5.817 - 6.198)
0.150 - 0.157** (3.810 - 3.988)
1 0.015 0.004 x 45 (0.38 0.10) 0.007 - 0.0098 (0.178 - 0.249) 0.016 - 0.050 (0.406 - 1.270) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP 0.053 - 0.068 (1.351 - 1.727)
23
4
56
7
8 0.004 - 0.0098 (0.102 - 0.249)
0.008 - 0.012 (0.203 - 0.305)
0.0250 (0.635) BSC
GN16 (SSOP) 1098
11
LTC1654
RELATED PARTS
PART NUMBER LTC1257 LTC1446/LTC1446L LTC1448 LTC1450/LTC1450L LTC1451 LTC1452 LTC1453 LTC1454/LTC1454L LTC1456 LTC1458/LTC1458L LTC1658 LTC1659 DESCRIPTION Single 12-Bit VOUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V, Reference Can Be Overdriven Up to 12V, i.e., FSMAX = 12V Dual 12-Bit VOUT DACs in SO-8 Package Dual 12-Bit VOUT DAC, VCC: 2.7V to 5.5V Single 12-Bit VOUT DACs with Parallel Interface Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V, Internal 2.048V Reference Brought Out to Pin Single Rail-to-Rail 12-Bit VOUT Multiplying DAC, VCC: 2.7V to 5.5V Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality Single Rail-to-Rail Output 12-Bit DAC with Clear Pin, Full Scale: 4.095V, VCC: 4.5V to 5.5V Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality 14-Bit Rail-to-Rail Micropower DAC in MSOP, VCC: 2.7V to 5.5V Single Rail-to-Rail 12-Bit VOUT DAC in 8-Pin MSOP, VCC: 2.7V to 5.5V COMMENTS 5V to 15V Single Supply, Complete VOUT DAC in SO-8 Package LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Output Swings from GND to REF. REF Input Can Be Tied to VCC LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V 5V, Low Power Complete VOUT DAC in SO-8 Package Low Power, Multiplying VOUT DAC with Rail-to-Rail Buffer Amplifier in SO-8 Package 3V, Low Power, Complete VOUT DAC in SO-8 Package LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Low Power, Complete VOUT DAC in SO-8 Package with Clear Pin LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Output Swings from GND to REF. REF Input Can Be Tied to VCC Low Power, Multiplying VOUT DAC in MS8 Package. Output Swings from GND to REF. REF Input Can Be Tied to VCC. Low Cost, 10ppm Drift Ultralow Drift 3ppm/C, Initial Accuracy: 0.04% Low Drift 10ppm/C, Initial Accuracy: 0.05%
References LT1460 LT1461 LT1634 Micropower Precision Reference Precision Voltage Reference Micropower Precision Reference
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
1654i LT/TP 0400 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2000

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